Thin Wafer (<30 µm)

For Stacking Dies, the final chip thickness is reduced to 30 µm and below. In production, however, these thicknesses cannot be achieved by grinding, especially since stress relief in high volume production becomes an important issue at 50 µm and below. The Cu-plugs for 3D-Interconnects require contact-free treatment without metal contamination. For this application PVA TePla offers the advanced technology of wafer thinning by smooth remote plasma etching. With excellent uniformity we can extend our stress relief process for thinning the wafer. The ASYNTIS 2.2 is designed for high throughput in this advanced market. Wafer Thinning can be applied in-situ with Stress Relief and Passivation.

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